? semiconductor components industries, llc, 2009 november, 2009 ? rev. 6 1 publication order number: mc74vhct74a/d mc74vhct74a dual d-type flip-flop with set and reset the mc74vhct74a is an advanced high speed cmos d ? type flip ? flop fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. the signal level applied to the d input is transferred to q output during the positive going transition of the clock pulse. reset (rd ) and set (sd ) are independent of the clock (cp) and are accomplished by setting the appropriate input low. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the inputs tolerate voltages up to 7.0 v, allowing the interface of 5.0 v systems to 3.0 v systems. the vhct inputs are compatible with ttl levels. this device can be used as a level converter for interfacing 3.3 v to 5.0 v, because it has full 5.0 v cmos level output swings. the vhct74a input structures provide protection when voltages between 0 v and 5.5 v are applied, regardless of the supply voltage. the output structures also provide protection when v cc = 0 v. these input and output structures help prevent device destruction caused by supply voltage ? input/output voltage mismatch, battery backup, hot insertion, etc. features ? high speed: f max = 60 mhz (typ) at v cc = 5.0 v ? low power dissipation: i cc = 2 a (max) at t a = 25 c ? power down protection provided on inputs ? balanced propagation delays ? designed for 4.5 v to 5.5 v operating range ? low noise: v olp = 0.8 v (max) ? pin and function compatible with other standard logic families ? latchup performance exceeds 300 ma ? esd performance: hbm > 2000 v; machine model > 200 v ? chip complexity: 128 fets or 32 equivalent gates ? pb ? free packages are available figure 2. logic diagram rd1 d1 cp1 sd1 rd2 d2 cp2 sd2 1 2 3 4 13 12 11 10 5 6 9 8 q1 q1 q2 q2 http://onsemi.com figure 1. pin assignment sd1 cp1 d1 rd1 11 12 13 14 8 9 10 5 4 3 2 1 7 6 sd2 cp2 d2 rd2 v cc q2 q2 gnd q1 q1 see detailed ordering and shipping information on page 3 of this data sheet. ordering information 1 1 1 14 vhct74ag awlyww 1 14 vhct 74a alyw marking diagrams soic ? 14 d suffix case 751a tssop ? 14 dt suffix case 948g function table inputs outputs sd rd cp d q q lh xx hl hl xx lh l l x x h* h* hh h hl hh l lh h h l x no change h h h x no change h h x no change *both outputs will remain high as long as set and reset are low, but the output states are unpredictable if set and reset go high simultaneously. a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb ? free package (note: microdot may be in either location)
mc74vhct74a http://onsemi.com 2 ??????????????????????? ??????????????????????? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? v cc ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ? 20 ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 20 ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 25 ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 50 ?? ?? ???? ???? ???? ?????????????? ?????????????? ?????????????? ?????? ?????? ?????? ?? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. ?derating ? soic packages: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c recommended operating conditions ???? ???? ??????????????????????? ??????????????????????? ???? ???? ???? ???? ?? ?? ???? ???? v cc ??????????????????????? ??????????????????????? ???? ???? ???? ???? ?? ?? ???? ???? ??????????????????????? ??????????????????????? ???? ???? ???? ???? ?? ?? ???? ???? ???? ??????????????????????? ??????????????????????? ??????????????????????? ???? ???? ???? ???? ???? ???? ?? ?? ?? ???? ???? ??????????????????????? ??????????????????????? ???? ???? ? 55 ???? ???? ?? ?? c ???? ???? ??????????????????????? ??????????????????????? 0.5 v ???? ???? ???? ???? ?? ?? ????????????????????????????????? ????????????????????????????????? dc electrical characteristics ???? ???? ?????????? ?????????? ??????? ??????? ??? ??? ?????? ?????? c ??????? ??????? ? 55 to 125 c ?? ?? ??? ??? ?? ???? ???? ???? ???? v ih ?????????? ?????????? ? level input voltage ??????? ??????? ??? ??? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ?? ?? ???? ???? ?????????? ?????????? ? level input voltage ??????? ??????? ??? ??? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ?? ?? ???? ???? ???? ???? ?????????? ?????????? ?????????? ?????????? ? level output voltage v in = v ih or v il ??????? ??????? ??????? ? 50 a ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? ?? ???? ???? ???? ???? ???? ???? ?? ?? ?? ?? ??????? ??????? ? 8 ma ??? ??? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ???? ???? ???? ?????????? ?????????? ?????????? ? level output voltage v in = v ih or v il ??????? ??????? a ??? ??? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ?? ?? ?? ??????? ??????? ??? ??? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ???? ???? ?????????? ?????????? ??????? ??????? ??? ??? ??? ??? ??? ??? ?? ?? 0.1 ???? ???? ???? ???? 1.0 ?? ?? a ???? ???? ?????????? ?????????? ??????? ??????? ??? ??? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ?? ?? a ???? ???? ???? ?????????? ?????????? ?????????? ??????? ??????? ??????? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? ?? ???? ???? ???? ???? ???? ???? ?? ?? ?? ???? ???? ?????????? ?????????? ??????? ??????? ??? ??? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ?? ?? a this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74vhct74a http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (input t r = t f = 3.0ns) ???? ???? ???? symbol ??????????? ??????????? ??????????? ???????? ???????? ???????? ?????? ?????? c ??????? ??????? ? 55 to 125 c ?? ?? ?? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ???? ???? t plh , t phl ??????????? ??????????? ???????? ???????? 0.5v c l = 15 pf c l = 50 pf ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ?? ?? ???? ???? ???? ??????????? ??????????? ??????????? ???????? ???????? ???????? 0.5v c l = 15 pf c l = 50 pf ??? ??? ??? ??? ??? ??? ?? ?? ?? ???? ???? ???? ???? ???? ???? ?? ?? ?? ???? ???? ???? ??????????? ??????????? ??????????? ???????? ???????? ???????? 0.5v c l = 15 pf c l = 50 pf ??? ??? ??? ??? ??? ??? ?? ?? ?? ???? ???? ???? ???? ???? ???? ?? ?? ?? ???? ???? ??????????? ??????????? ???????? ???????? ??? ??? ??? ??? ?? ?? ???? ???? ???? ???? ?? ?? typical @ 25 c, v cc = 5.0 v pf 24 1. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc / 2 (per flip ? flop). c pd is used to determine the no ? load dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc . timing requirements (input t r = t f = 3.0 ns) ???? ???? ???? symbol ???????????????? ???????????????? ???????????????? ???? ???? ???? ??????????? ??????????? ?? ?? ?? ????? ????? c ??????? ??????? ? 55 to 125 c ???? ???? t w ???????????????? ???????????????? ???? ???? 0.5 ????? ????? ??????? ??????? ?? ?? ???? ???? ???????????????? ???????????????? ???? ???? 0.5 ????? ????? ??????? ??????? ?? ?? ???? ???? ???????????????? ???????????????? ???? ???? 0.5 ????? ????? ??????? ??????? ?? ?? ???? ???? ???????????????? ???????????????? ???? ???? 0.5 ????? ????? ??????? ??????? ?? ?? ???? ???? ???????????????? ???????????????? ???? ???? 0.5 ????? ????? ??????? ??????? ?? ?? ordering information device package shipping ? mc74vhct74ad soic ? 14 55 units / rail MC74VHCT74ADR2 soic ? 14 2500 / tape & reel MC74VHCT74ADR2g soic ? 14 (pb ? free) 2500 / tape & reel mc74vhct74adt tssop ? 14* 96 units / rail mc74vhct74adtr2 tssop ? 14* 2500 / tape & reel mc74vhct74adtr2g tssop ? 14* 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc74vhct74a http://onsemi.com 4 figure 3. switching waveform figure 4. switching waveform 1.5 v 1.5v v cc 1.5v v cc 1.5v 3 v 3 v gnd gnd sd or rd q or q q or q cp t plh t phl 1.5 v d cp 3 v 3 v gnd figure 5. switching waveform valid gnd t su t h t rec t w *includes all probe and jig capacitance c l * test point device under test output figure 6. switching waveform 1/f max cp q or q 3v gnd 1.5 v 1.5 v t plh t phl t w 1.5 v figure 7. input equivalent circuit input v oh v ol 3v gnd
mc74vhct74a http://onsemi.com 5 package dimensions soic ? 14 d suffix case 751a ? 03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc74vhct74a http://onsemi.com 6 package dimensions tssop ? 14 dt suffix case 948g ? 01 issue a dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc74vhct74a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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